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<p>This typedef contains configuration information for the DisplayPort Receiver Subsystem core.  
 <a href="struct_x_dp_rx_ss___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a97e296a5d464e36bb8d0a77cbf0a390c"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a97e296a5d464e36bb8d0a77cbf0a390c">DeviceId</a></td></tr>
<tr class="memdesc:a97e296a5d464e36bb8d0a77cbf0a390c"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the DisplayPort RX Subsystem core.  <a href="#a97e296a5d464e36bb8d0a77cbf0a390c">More...</a><br/></td></tr>
<tr class="separator:a97e296a5d464e36bb8d0a77cbf0a390c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51ebda7704c9682d7b8fc8073da88ad8"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a51ebda7704c9682d7b8fc8073da88ad8">BaseAddress</a></td></tr>
<tr class="memdesc:a51ebda7704c9682d7b8fc8073da88ad8"><td class="mdescLeft">&#160;</td><td class="mdescRight">BaseAddress is the physical base address of the core's registers.  <a href="#a51ebda7704c9682d7b8fc8073da88ad8">More...</a><br/></td></tr>
<tr class="separator:a51ebda7704c9682d7b8fc8073da88ad8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4aabc3c437ecdf3160ba536f4aad429"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#aa4aabc3c437ecdf3160ba536f4aad429">SecondaryChEn</a></td></tr>
<tr class="memdesc:aa4aabc3c437ecdf3160ba536f4aad429"><td class="mdescLeft">&#160;</td><td class="mdescRight">This Subsystem core supports audio packets being sent by the secondary channel.  <a href="#aa4aabc3c437ecdf3160ba536f4aad429">More...</a><br/></td></tr>
<tr class="separator:aa4aabc3c437ecdf3160ba536f4aad429"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae80171eefe19931e1ff223e570f1824c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#ae80171eefe19931e1ff223e570f1824c">MaxNumAudioCh</a></td></tr>
<tr class="memdesc:ae80171eefe19931e1ff223e570f1824c"><td class="mdescLeft">&#160;</td><td class="mdescRight">The total number of Audio channels supported by this core instance.  <a href="#ae80171eefe19931e1ff223e570f1824c">More...</a><br/></td></tr>
<tr class="separator:ae80171eefe19931e1ff223e570f1824c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a18d32ddf160bf0b9022cc29bb9fa2d"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a7a18d32ddf160bf0b9022cc29bb9fa2d">MaxBpc</a></td></tr>
<tr class="memdesc:a7a18d32ddf160bf0b9022cc29bb9fa2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum bits/color supported by this Subsystem core.  <a href="#a7a18d32ddf160bf0b9022cc29bb9fa2d">More...</a><br/></td></tr>
<tr class="separator:a7a18d32ddf160bf0b9022cc29bb9fa2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6dabb89d18ef5262ca4b527804923365"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a6dabb89d18ef5262ca4b527804923365">HdcpEnable</a></td></tr>
<tr class="memdesc:a6dabb89d18ef5262ca4b527804923365"><td class="mdescLeft">&#160;</td><td class="mdescRight">This Subsystem core supports digital content protection.  <a href="#a6dabb89d18ef5262ca4b527804923365">More...</a><br/></td></tr>
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<tr class="memitem:a047730675b73e61d032c00a7c4e35cdd"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a047730675b73e61d032c00a7c4e35cdd">MaxLaneCount</a></td></tr>
<tr class="memdesc:a047730675b73e61d032c00a7c4e35cdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum lane count supported by this core instance.  <a href="#a047730675b73e61d032c00a7c4e35cdd">More...</a><br/></td></tr>
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<tr class="memitem:af6d4fd56bf410f4f04b6e5bc6c66a8fd"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#af6d4fd56bf410f4f04b6e5bc6c66a8fd">MstSupport</a></td></tr>
<tr class="memdesc:af6d4fd56bf410f4f04b6e5bc6c66a8fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi-stream transport (MST) mode is enabled by this core instance.  <a href="#af6d4fd56bf410f4f04b6e5bc6c66a8fd">More...</a><br/></td></tr>
<tr class="separator:af6d4fd56bf410f4f04b6e5bc6c66a8fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0acbe5bd683af0f65f4192a8280288be"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a0acbe5bd683af0f65f4192a8280288be">NumMstStreams</a></td></tr>
<tr class="memdesc:a0acbe5bd683af0f65f4192a8280288be"><td class="mdescLeft">&#160;</td><td class="mdescRight">The total number of MST streams supported by this core instance.  <a href="#a0acbe5bd683af0f65f4192a8280288be">More...</a><br/></td></tr>
<tr class="separator:a0acbe5bd683af0f65f4192a8280288be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1783e6e0b59b36314ec3a874cd58d6e7"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a1783e6e0b59b36314ec3a874cd58d6e7">ColorFormat</a></td></tr>
<tr class="memdesc:a1783e6e0b59b36314ec3a874cd58d6e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of color format supported by this core instance.  <a href="#a1783e6e0b59b36314ec3a874cd58d6e7">More...</a><br/></td></tr>
<tr class="separator:a1783e6e0b59b36314ec3a874cd58d6e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb687e5c8ca0d9f94d97f302b65f9427"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_dp_rx_ss___dp_sub_core.html">XDpRxSs_DpSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#abb687e5c8ca0d9f94d97f302b65f9427">DpSubCore</a></td></tr>
<tr class="memdesc:abb687e5c8ca0d9f94d97f302b65f9427"><td class="mdescLeft">&#160;</td><td class="mdescRight">DisplayPort Configuration.  <a href="#abb687e5c8ca0d9f94d97f302b65f9427">More...</a><br/></td></tr>
<tr class="separator:abb687e5c8ca0d9f94d97f302b65f9427"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1503a7da8b668879f291553428cd8a04"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_dp_rx_ss___iic_sub_core.html">XDpRxSs_IicSubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dp_rx_ss___config.html#a1503a7da8b668879f291553428cd8a04">IicSubCore</a></td></tr>
<tr class="memdesc:a1503a7da8b668879f291553428cd8a04"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Configuration.  <a href="#a1503a7da8b668879f291553428cd8a04">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains configuration information for the DisplayPort Receiver Subsystem core. </p>
<p>Each DisplayPort RX Subsystem core should have a configuration structure associated. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a51ebda7704c9682d7b8fc8073da88ad8"></a>
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<p>BaseAddress is the physical base address of the core's registers. </p>

<p>Referenced by <a class="el" href="xdprxss__debug__example_8c.html#a1ba81c8bc9e52facf98dbea2915e557d">DpRxSs_DebugExample()</a>, <a class="el" href="xdprxss__hdcp__example_8c.html#a33c9dce40424c29784819adc27eaf94e">DpRxSs_HdcpExample()</a>, <a class="el" href="xdprxss__intr__example_8c.html#aa3b5b709da2f704130f76b2cb237952c">DpRxSs_IntrExample()</a>, <a class="el" href="xdprxss__mst__example_8c.html#a4ee6ff10963ea3a0f8d8e340983a5a99">DpRxSs_MstExample()</a>, <a class="el" href="xdprxss__selftest__example_8c.html#a1aca85908f837f0659efe764a4216c3d">DpRxSs_SelfTestExample()</a>, and <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>.</p>

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<p>Type of color format supported by this core instance. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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          <td class="memname">u16 XDpRxSs_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the DisplayPort RX Subsystem core. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_dp_rx_ss___dp_sub_core.html">XDpRxSs_DpSubCore</a> XDpRxSs_Config::DpSubCore</td>
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<p>DisplayPort Configuration. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>.</p>

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          <td class="memname">u8 XDpRxSs_Config::HdcpEnable</td>
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<p>This Subsystem core supports digital content protection. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>, <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>, <a class="el" href="group__dprxss.html#gaf724dbd61d196f9bd1a8060f1f73816d">XDpRxSs_Reset()</a>, and <a class="el" href="group__dprxss.html#ga9a5414c99d822a3848b6ef7442fe551d">XDpRxSs_SelfTest()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_dp_rx_ss___iic_sub_core.html">XDpRxSs_IicSubCore</a> XDpRxSs_Config::IicSubCore</td>
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<p>IIC Configuration. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>.</p>

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<p>The maximum bits/color supported by this Subsystem core. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>, and <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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<p>The maximum lane count supported by this core instance. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>, and <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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          <td class="memname">u8 XDpRxSs_Config::MaxNumAudioCh</td>
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<p>The total number of Audio channels supported by this core instance. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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<p>Multi-stream transport (MST) mode is enabled by this core instance. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>, and <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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<p>The total number of MST streams supported by this core instance. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga25f3b6123ff5cbf277c4117617980738">XDpRxSs_CfgInitialize()</a>, <a class="el" href="group__dprxss.html#ga65886916bf0be3e73f4d718ec087c6f5">XDpRxSs_ExposePort()</a>, and <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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<p>This Subsystem core supports audio packets being sent by the secondary channel. </p>

<p>Referenced by <a class="el" href="group__dprxss.html#ga5bcda88f1e979aa99b8a903a12e421fc">XDpRxSs_ReportCoreInfo()</a>.</p>

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